1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus including a redundancy circuit.
2. Related Art
In general, if a semiconductor apparatus has a defective memory cell, the semiconductor apparatus may replace a defective memory cell with an available redundant memory cell.
After a wafer manufacturing process for the semiconductor apparatus is completed, the defective memory cell may be detected by a test operation, and replacement of the defective memory cell may be perform by cutting a fuse.
According to a known art, when a redundancy circuit for cutting the fuse is employed in a semiconductor apparatus, positional information, e.g., a fuse-cut row or column address of a previous defective memory cell is stored to replace the defective memory cell with a redundancy memory cell.
Recently, various electronic devices are being developed to meet requirements for miniaturization, low power consumption, and a low price. Accordingly, semiconductor apparatuses are also being developed toward mass storage, high speed, low power, and new additional functions, and efforts to highly integrate the semiconductor devices continue.
However, if a large number of fuses are required, circuit configuration and wiring may be complicated.
Also, if the number of fuses is reduced to increase the number of die per wafer, the repair efficiency may decrease.